Grants and Contributions:

Title:

Further Development and Evaluation of an Automated Image Analysis Pipeline for Semiconductor Circuit Reverse Engineering

Agreement Number:

EGP2

Agreement Value:

$12,500.00

Agreement Date:

May 10, 2017 -

Organization:

Natural Sciences and Engineering Research Council of Canada

Location:

Ontario, CA

Reference Number:

GC-2017-Q1-00563

Agreement Type:

Grant

Report Type:

Grants and Contributions

Additional Information:

Grant or Award spanning more than one fiscal year. (2017-2018 to 2018-2019)

Recipient's Legal Name:

Ukwatta, Eranga (Carleton University)

Program:

Engage Plus Grants for Universities

Program Purpose:

The objective of this proposal is to develop a software tool consisting of a suite of image analysis techniques tox000D
help automate the detection of patents infringement related to circuitry in integrated circuits (ICs). Ourx000D
proposed software will aid in automating the process of circuit extraction, where an IC is reverse engineered tox000D
determine the exact construction and design of its electronic circuitry. Circuit extraction is sometimes requiredx000D
to determine infringement of patent(s). The process of circuit extraction is performed by individually removingx000D
layers of circuitry of an IC, imaging the layers using a scanning electron microscope (SEM), and analysingx000D
SEM images of the IC layout to reconstruct the circuit schematics. One of the main bottlenecks in the existingx000D
approach is the accurate segmentation of the precise IC layout from SEM images, because minute errors inx000D
segmentation usually lead to significant errors in the reconstructed IC schematics. Image intensityx000D
threshold-based methods, such as the one used currently by TechInsights to segment the SEM images tends tox000D
perform poorly under image noise, requires tedious manual inspection and correction and consequently resultsx000D
in increased production costs. In the previous NSERC Engage project, we developed an image-analysisx000D
pipeline, which consisted of an image normalization method, two image filters and two image segmentationx000D
methods for wires and vertical interconnect accesses (VIAs). The preliminary results indicated that thex000D
segmentation results obtained using the developed pipeline, as compared to the methods currently used byx000D
TechInsights, provided more accurate segmentations of the IC layout. In this proposed NSERC Engage Plusx000D
project, we will expand the recently developed pipeline to address the following remaining challenges: 1)x000D
utilizing not only SEM images created using backscattered electrons, but also the ones created using secondaryx000D
electrons; 2) requiring two separate algorithms for segmenting wires and VIAs lead to inferior results due tox000D
image artifacts; 3) choosing optimized parameters for a given SEM image dataset; and 4) the longx000D
computational time of the level set segmentation method. We will develop a multi-region segmentation method