Grants and Contributions:

Grant or Award spanning more than one fiscal year. (2017-2018 to 2022-2023)

The goal of this research is to reduce the power consumption of FPGAs to the level of the lowest power consuming processors through the use of run-time reconfiguration. Run-time reconfiguration, the ability of an FPGA to change its functionality while under operation, has been successfully used in many commercial FPGAs to expand the logic capacity of FPGAs to beyond what can be manufactured by current silicon process technologies. For portable devices with limited battery power, however, the logic capacity of an FPGA is not limited by current process technologies but by the low power output of small batteries. Run-time reconfiguration potentially can allow FPGAs to gracefully trade performance for reduced power consumption in order to bring the power consumption of current low power FPGAs to the level of the lowest power consuming processors.
FPGAs are an important platform for implementing a variety of digital applications due to their short time to market, re-programmability and low non-recurring engineering costs. While FPGAs have been successfully used in many applications including digital signal processing, aerospace, medical imaging, computer vision, speech recognition, and ASIC prototyping, they have not been widely used in mobile applications due to their high static power consumption. In particular, the static power consumption of today’s low power FPGAs is significantly higher than the static power consumption of the lowest power consuming processors. Consequently, constrained by the limited power output of small batteries, current mobile devices are mainly limited to the use of low-power processors despite the fact that these processors have extremely low performance and energy efficiency especially when compared to FPGAs.
In this work, we will characterize the effect of run-time reconfiguration on the area, performance, and power efficiency of FPGAs. In particular, we will develop new FPGA area and performance models to accurately measure the effect of run-time reconfiguration on the performance, dynamic and static power consumption of FPGAs. We will then develop new FPGA architectures and tools to effectively utilize run-time reconfiguration under the power constraint of mobile applications and empirically evaluate the effect of run-time reconfiguration on the area, performance and power efficiency of low power FPGAs.